The 11C90 and 11C91 are high-speed prescaler designed specifically for communication and instrumentation applications. All discussions and examples in this data sheet apply to the 11C91 as well as the 11C90.
The 11C90 will divide by 10 or 11 and the 11C91 by 5 or 6, both over a frequency range from DC to typically 650MHz. The division ratio is controlled by the Mode Control. The divide-by-10 or -11 capability allows the use of pulse swallowing techniques to control high-speed counting modulus by lower-speed circuits. The 11C90 may be used with either ECL or TTL power supplies.
In addition to the ECL outputs Q and Q, the 11C90 contains an ECL-to-TTL converter and a TTL output. The TTL output operates from the same VCC and VEE levels as the counter, but a separate pin is used for the TTL circuit VEE. This minimises noise coupling when the TTL output switches and also allows power consumption to be reduced by leaving the separate VEE pin open if the TTL output is not used.
To facilitate capacitive coupling of the clock signal, a 400Ω resistor (VREF) is connected internally to the VBB reference. Connecting this resistor to the Clock Pulse input (CP) automatically centres the input about the switching threshold. Maximum frequency operation is achieved with a 50% duty cycle. Each of the Mode Control inputs is connected to an internal 2kΩ resistor with the other end uncommitted (RM1 and RM2). An M input can be driven from a TTL circuit operating from the same VCC by connecting the free end of the associated 2kΩ resistor to VCCA. When an M input is driven from the ECL circuit, the 2kΩ resistor can be left open or, if required, can be connected to VEE to act as a pull-down resistor.
The 11C90 contains four ECL Flip-Flops, an ECL to TTL converter and a Schottky TTL output buffer with an active pull-up. Three of the Flip-Flops operate as a synchronous shift counter driving the fourth Flip-Flop operating as an asynchronous toggle. The internal feedback logic is such that the TTL output and the Q ECL output are HIGH for six clock periods and LOW for five clock periods. The Mode Control (M) inputs can modify the feedback to make the output HIGH for five clock periods and LOW for five clock periods, as indicated in the Count Sequence Table.
The feedback logic is such that the instant the output goes HIGH, the circuit is already committed as to whether the output period will be 10 or 11 clock periods long. This means that subsequent changes in an M input signal, including decoding spikes, will have no effect on the current output period. The only timing restriction for an M input signal is that it be in the desired state at least a setup time before the clock that follows the HHLL state shown in the table. The allowable propagation delay through external logic to an M input is maximised by designing it to use the positive transition of the 11C90 output as its active edge. This gives an allowable delay of ten clock periods, minus the CP to Q delay of the 11C90 and the M to CP setup time. If the external logic uses the negative output transition as its active edge, the allowable delay is reduced to five clock periods minus the previously mentioned delay and setup time.
Capacitively coupled triggering is simplified by the 400Ω resistor which connects pin 15 to the internal VBB reference. By connecting this to the CP input, as shown in Figure 3, the clock is automatically centred about the input threshold. A clock duty cycle of 50% provides the fastest operation since the Flip-Flops are Master-Slave types with offset clock thresholds between master and slave. This feature ensures that the circuit will operate with clock waveforms having very slow rise and fall times, and thus, there is no maximum frequency restriction. Recommended minimum and maximum clock amplitude as a function of a frequency and temperature are shown in the graph labelled Figure 2. When the CP or any other input is driven by another ECL circuit, typical ECL termination methods are recommended.
When an M input is to be driven from a TTL output operating from the same VCC and ground (VEE), the internal 2kΩ resistor can be used to pull the TTL output up as shown in Figure 5. Some types of TTL outputs will only pull up to within two diode drops of VCC, which is not high enough for 11C90 inputs. The resistor will pull the signal up through the threshold region, although this final rise may be somewhat slow, depending on wiring capacitance.
The ECL outputs have no pull-down resistors and can drive series or parallel terminated transmission lines. For short interconnections that do not require impedance matching, a 270Ω to 510Ω resistor to VEE can be used to establish the VOL level. Both VCC pins must always be used and should be connected together as close to the package as possible. Pin 12 must always be connected to the VEE side of the supply, while pin 13 is required if the TTL output is used. Low impedance VCC and VEE distribution and RF by-pass capacitors are recommended to prevent crosstalk.