FX209 Delta Modulator

The FX209 contains all the active analogue and digital circuitry of an adaptive delta modulation encoder or decoder, leaving the user to connect the passive resistors and capacitors to suit his application.
This Nitride PMOS device can in many applications replace conventional analogue-to-digital converters (ADC) and their corresponding digital-to-analogue converters (DAC) with advantage.
The conventional ADC is a pulse code modulator. It accepts a continuous band limited signal, samples it, and converts each sample into a binary word. This means that for n bit binary words the samples have been quantized to any of 1 levels, where 1=2ⁿ.
The binary words are then sequentially transmitted, in the case of a telecommunications application, or they may be used locally in some digital process, such as a digital filter. There are three characteristics of this type of ADC which in some applications can give rise to difficulties.

• The necessity of maintaining word synchronism, i.e. the ability of the receiver to identify each code word correctly. If this is not done the DAC will decode words composed of two adjacent words, resulting in gross distortion.
• The need to provide a filter with a sharp cut-off after the DAC to prevent aliasing effects.
• In situations where some of the binary words at the input to the DAC are in error, due to a noisy transmission channel, for example, the signal to noise ratio SNR of the decoded signal is exponentially related to the number of words in error. This means that a small error rate results in a large reduction in SNR.

The FX-209 adaptive delta modulator, ADM, greatly alleviates these difficulties encountered with conventional ADCs and DACs. Before describing the FX-209, the basic behaviour of the linear and adaptive delta modulators are briefly explained.

The linear delta modulator is shown in Figure 1. The continuous input signal x(t) to be encoded is compared with the feedback signal y(t) to yield the binary signal q(t). This signal is converted into a synchronous binary signal L(t) with the aid of a D flip-flop and an external clock. L(t) is transmitted (or processed, if, for example, the delta modulator forms part of an instrument), and it is also locally decoded back into a continuous signal y(t) using a simple R1 C1 integrator. The action of the encoder is to cause y(t) to track x(t).
Notice that at any clock instant the polarity of the output bit is dependent on the sign of the error x(t) - y(t), and this is the information transmitted. This means that word synchronisation, essential with conventional ADCs, is not required. However, the bit rate is not reduced because the clock operates at a higher value than in a conventional ADC. This results in a simplification of the requirements of the final filter after the decoder, as at these high clock rates aliasing is not a problem.
The delta modulator decoder is very simple, see Figure 1(b). It is the local decoder used in the encoder, which in the absence of transmission errors recovers y(t), followed by a low pass filter to remove the sharp changes in this waveform thereby producing x(t), a close replica of x(t). The size of a single transmission error produces an error in y(t) of approximately twice the step height γ, see Figure 2, but this error in y(t) can propagate for a duration depending on the time constant of the R1 C1 integrator. By comparison, the errors in conventional ADCs can be very much greater although they do not propagate. However, for speech signals, linear and syllabically companded delta modulation systems are vastly superior to pulse code modulation systems (which of course comprise an ADC and a DAC) in the presence of high transmission error rates.

The tracking ability of the delta modulator can be greatly enhanced if the changes γ in the feedback signal per clock instant adapts to the variations of the input signal.
The choice of adaptation strategy depends on the type of signal being encoded, and the FX-209 is particularly suitable for encoding speech signals. It is found that a desirable adaptation procedure is for γ to vary in a manner dependent on the envelope of the speech signal, rather than its instantaneous value. The figure shows a syllabically companded delta modulator. The titles ‘companded’ and ‘adaptive’ may be treated synonymously. The R1 C1 integrator is included as before to convert the pulses (whose duration is equal to a clock period) in the waveform h(t) into the continuous signal y(t) as previously described.
Although L(t) is a binary waveform, h(t) the signal at the output of the multiplier, is a multilevel one, whose magnitude depends on Vc(t) and whose polarity is identical to L(t).
The magnitude H of the pulses in h(t) is
H = A Vc(t) {L(t)}
where A is a gain factor. The sequence detector observes the present and previous values of L(t), say Lr, Lr-1 and Lr-2, and the logic circuitry produces a waveform g(t) which either increases or decreases the charge on capacitor C2. A suitable encoding algorithm is one which makes g(t) a logical one if the encoder is experiencing a partial overload, i.e. if the logical equation
Lr Lr-1 Lr-2 + Lr Lr-1 Lr-2 = 1
is satisfied. The time constant R2 C2 (>>R1 C1) is chosen as a function of the envelope of the input signal. In the case of speech, a suitable choice of R2 C2 is 5 to 20 ms, although sometimes 100 ms may be preferred.
Observe that if the envelope of x(t) increases g(t) will charge up C2 and h(t) will be composed of large pulses, and vice versa if the envelope of x(t) is small. It is because the amplitude of h(t) changes slowly relative to the clock rate that this type of delta modulator is relatively resistant to transmission errors.
The L(t) signal is decoded at the receiver by applying it to the local decoder (the same form as the one used in the encoder) followed by a low pass filter to remove out-of-band noise.

The system diagram of the FX-209 used as an adaptive delta modulator is shown in Figure A. It resembles the syllabically companded delta modulator shown in Figure 3, except that an idle channel loop containing resistor R5 and adaptation algorithm Z1, Z2, Z3 have been added.
The idle channel feedback path between pins 14 and 13 reduces the idle channel noise which occurs in the decoded signal when the input signal x(t) is zero. Ideally, when x(t) = 0, L(t) should be composed of alternate positive and negative levels, i.e. a logical pattern ....101010.... The final low pass filter F₀ having a cut-off frequency well below the high-frequency oscillations in L(t), produces a zero output voltage. In practice, the idle channel pattern will diverge from the alternating pattern, and a small signal will emerge from the filter F₀. The time constant R5 C'in, (R5>>R4) is chosen so as to make the pattern of logical ones and zeros close to the ideal. By arranging for R5 C'in >> f_CI the lowest frequency to be encoded, the idle channel loop does not interfere with the encoding of the speech signals. R4 and R5 are selected to provide the correct input bias such that the input signal can be varied over the widest amplitude range without waveform distortion occurring. For D.C. operation, or when FX-209 acts as a decoder, R5 and C'in are removed.
The R1 C1 integrator controls the overload characteristic shown in Figure 5. This characteristic shows the highest amplitude E_sm as an input sinusoid can have without causing the delta modulator to be overloaded. The overload condition is represented by:
E_sm=2.2/√(1+(f/f1)2) where f1=1/(2πR1C1)
f1 is the break frequency of the R1 C1 integrator.
If the signal x(t) to be encoded has a flat spectrum, then an R1 C1 integrator should be connected before C'in, and a corresponding differentiating network introduced between the FX-209 decoder and the filter F₀. The R1 C1 values used in Figure 5 are suitable for speech encoding.
The time constant R2 C2 is related to the envelope of the input signal. In the case of speech signals, R2 C2 may be set as a function of syllabic or pitch durations. Having selected R2 C2, R5 is chosen by applying sine wave and observing the locally decoded waveform on pin 11, and the symmetry of the pulses at pin 10. The choice of R3 is significant for large amplitude sinusoids. The lower R3, the better the symmetry of H and the decoded waveform in overload but lower amplitudes will overload the encoder. The compromise depends on the application. It is important to ensure that the FX-209 decoder (see figure 7) have the same resistor and capacitor values to ensure the similarity between the signals on pin 11 of the FX-209 encoder and decoder.
By adjusting Z1, Z2 and Z3 to either logical zero (ground) or a logical one (open-circuit) the logical signal g(t) can be altered for a given binary output signal L(t) according to table 1.
The significance of the symbols D and P in this table is as follows:
g(t) goes positive (earth) on the next negative going clock edge after D consecutive logical ones or logical zeros in the L(t) signal. g(t) returns to a negative potential on the Pth positive clock edge after a change of binary level in the L(t) signal. For the purpose of explanation, figure 6 is presented showing stylised g(t) waveforms for some D and P values and an arbitrary signal L(t). Observe that L(t) changes level on a positive going clock edge.

The FX-209 connected as a delta modulator decoder is shown in Figure 7. The idle channel loop is disconnected, and the binary signal L(t) is connected directly to the input comparator to remove the effects of amplitude noise and distortion introduced into the transmission channel. y(t) has been connected to pin 12 to utilise the buffer amplifier connected internally between pins 12 and 13. This arrangement is satisfactory, except when y(t) is very small. When it is important to faithfully decode small signals, connect y(t) directly to the filter, and provide a bias of no volts on pin 12. The values of resistors, capacitors, Z1, Z2, Z3, should be the same as those used in the encoder.

The FX-209 can be adapted to perform as a linear delta modulator by leaving pins 6 and 8 unconnected and applying -5 volts to pin 9. Using the Z1, Z2, Z3 resistor and capacitor values previously stated, the SNR versus input power for a White Gaussian signal is shown in Figure 15 for fp=64KHz. The characteristic improvement in SNR of 6dB per octave increase in input power is obtained.