SP8647 250MHz ÷ 10/11 Counter

250 MHz Variable Modulus Divider

  • SP8647 250MHz Counter PLESSEY
  • SP8647B 250MHz Counter PLESSEY


  • ECL Compatible Inputs/Outputs
  • Open Collector TTL/CMOS Output
  • AC Coupled Input (External Bias)

Quick Reference

  • Supply Voltage Vcc-Vee : 5.2V ± 0.25V
  • Power Consumption: 260mW
  • Temperature Range:
    • -55°Cto+125°C(A Grade)
    • -30°C to +70°C (B Grade)


The SP8647 is an ECL variable modulus divider, with ECL 10K and TTL/CMOS compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high state and by 11 when both are low (or open circuit).
The two clock inputs are interchangeable and either will act as a clock inhibit when connected to an ECL high level.
Normally, one input is left open circuit and the other is AC coupled, with externally-applied bias.

Operating Notes

  1. The clock and control inputs are ECL III compatible. There is an internal pulldown resistor to Vee of 4.3k on each input and therefore any unused input can be left open circuit. If it is desirable to capacitively couple the signal source to the clock then an external bias is required as shown in Fig. 6. The external bias voltage should be -1.3V at 25°C.
  2. The outputs are compatible with ECL II but can be interfaced to ECL 10K as shown in Fig. 8.
  3. The circuit will operate down to DC but slew rate must be better than 100V/µs.
  4. Input impedance is a function of frequency. See Fig. 5.
  5. The TTL/CMOS O/P is a free collector, with an output rise/fall time which is a function of load resistance and load capacitance. The load capacitance should therefore be kept to a minimum and the load resistance should not be too small otherwise VOL will be too great, eg TTL output current = 8mA VOL = 0.5V. For CMOS outputs, the value of load resistor should be the maximum consistent with satisfactory rise times.
  6. All components should be suitable for the frequency in use.

This sample has a white ceramic case and golden pins.