SP8691 Counter

SP8691 200 MHz Divide by 8/9 Counter

SP8691 200MHz Counter Plessey


  • Low-Frequency Operation
  • ECL and TTL/CMOS Outputs
  • AC Coupled Input
  • Temperature Ranges: -55°C to +125°C

Quick Reference Data

  • Supply Voltage: +5.0V
  • Power Consumption: 70mW
  • Maximum Input Frequency: 200MHz


The SP8691a is a low power ECL counter with both ECL 10K and TTL-compatible outputs. They divide by 8 when either control input in the high state and by 9 when both are low (or open circuit).

Operating Notes

  1. The clock inputs can be single or differentially driven. The clock input is biased internally and is coupled to the signal source with a suitable capacitor. The input signal path is completed by an input reference decoupling capacitor which is connected to earth.
  2. In the absence of a signal the device will self-oscillate. If this is undesirable it may be prevented by connecting a 68k resistor from the input to Vee (i.e. Pin 1 or 16 to Pin 12). This reduces input sensitivity by approximately 100mV.
  3. The circuit operates down to DC, but slew rate must be better than 100V/µs.
  4. The Q4 and Q4 outputs are compatible with ECL II but can be interfaced to ECL 10K.
  5. The PE inputs are ECL III/10K compatible and include a 10k internal pulldown resistor. Unused inputs can therefore be left open circuit.
  6. The input impedance of the SP8691 varies as a function of frequency.
  7. The TTL/CMOS output has a free collector and the high state output voltage will depend on the supply that the collector load is taken too. This should not exceed 12V.
  8. The rise/fall time of the open collector output waveform is directly proportional to load capacitance and load resistor value. Therefore load capacitance should be minimised and the load resistor kept to a minimum compatible with system power requirements.