SP8703 Counter

SP8703 1 GHz divide by 128/129 Counter

SP8703 Two modulus Counter Plessey


  • DC to 1 GHz Operation
  • -30° to +70°C Temperature Range
  • Unique Power-Down Feature
  • CMOS Compatible Output

Quick Reference Data

  • Supply Voltage 5.0V ± 0.25V
  • Supply Current 30mA typical
  • Storage temperature range: -55°C to +150°C


The SP8703 is a divide by 128/129 programmable divider with a maximum specified operating frequency of 1GHz.
The signal (clock) inputs are biased internally and require to be capacitor coupled.
The output stage is CMOS compatible only, the 0 to 1 output edge giving maximum loop delay.
A unique 'power-down' feature is included to minimise power consumption.


  1. The inputs are biased internally and coupled to a signal source with suitable capacitors.
  2. If no signal is present the devices will self-oscillate. If this is undesirable it may be prevented by connecting a 15k resistor from one input to pin 4 (ground). This will reduce the sensitivity.
  3. The circuits will operate down to DC but slew rate must be better than 100V/µs.
  4. The output stage is of an unusual design and is intended to interface with CMOS. External pull-up resistors or circuits must not be used.