SP8720 Counter

SP8720 300 MHz divide by 3/4 Counter

SP8720 300MHz Counter Plessey


The SP8720 is an ECL two-modulus divider with ECL10K compatible outputs. It divides by three when either of the ECL control inputs, PE1 or PE2, is in the high state and by four when both are low (or open circuit). An AC coupled input of 600mVp-p is required.


  • ECL Compatible Outputs
  • AC Coupled Inputs (Internal Bias)
  • Control inputs ECLIII/10K Compatible

Quick Reference Data

  • Supply Voltage: -5.2V
  • Power Consumption: 240mW
  • Operating temperature range:
    -55°C to +125°C (A Grade)
     30°C to +70°C (B Grade)

Operating Notes

  1. The clock input is biased internally and is coupled to the signal source with a suitable capacitor. The input signal path is completed by an input reference decoupling capacitor which is connected from pin 16 to earth.
  2. With no signal present, the device self-oscillate. If this is undesirable, it may be prevented by connecting a 15kΩ resistor from the input to Vee. This reduces the input sensitivity by approximately 100mV.
  3. The circuit operates down to DC, but slew rate must be better than 100V/µs.
  4. The Q outputs are compatible with ECL II but can be interfaced to ECL 10K. There is an internal circuit equivalent to a load of 2kΩ pulldown resistor at load output.
  5. The PE inputs are ECL III/10K compatible and include a 4.3kΩ internal pulldown resistor. Unused inputs can, therefore, be left open circuit.
  6. The input impedance of the SP8720 varies as a function of frequency.
  7. All components should be suitable for the frequency in use.