SP8740 Counter

SP8740 300 MHz divide by 5/6 Counter

SP8740 300MHz Counter Plessey

Description

The SP8740 and SP8741 are ECL counters with ECL 10K compatible output. The SP8740/SP8741 divide by 5 and 6 respectively when either control input is in the high state and by 6 and 7 respectively when both inputs are in the low state (or open circuit). An AC coupled input of 600mV is required.

Features

  • ECL Compatible Outputs
  • ECL Compatible Control Inputs
  • AC Coupled Inputs (Internal Bias)

Quick Reference Data

  • Supply Voltage: -5.2V
  • Power Consumption: 240mW
  • Storage temperature range: -55°C to +150°C

Operating

  1. The clock input is biased internally and is coupled to the signal source with a suitable capacitor. The input signal path is completed by an input reference decoupling capacitor which is connected to earth.
  2. With no signal present, the device self-oscillate. If this is undesirable, it may be prevented by connecting a 15kΩ resistor from the input to Vee (i.e. Pin 1 to Pin 12). This reduces the input sensitivity by approximately 100mV.
  3. The circuit operates down to DC, but slew rate must be better than 100V/µs.
  4. The Q outputs are compatible with ECL II but can be interfaced to ECL 10K. There is an internal circuit equivalent to a load of 2kΩ pulldown resistor at load output.
  5. The PE inputs are ECL III/10K compatible and include a 4.3kΩ internal pulldown resistor. Unused inputs can, therefore, be left open circuit.
  6. The input impedance of the SP8740/1 varies as a function of frequency. The SP8740 is not suitable for use in a fixed divide by 6 mode.