ZN427 8-BIT DAC

Features

• Easy Interfacing to Microprocessor, or Operates as a 'Stand-Alone' Converter
• Fast: 10 microseconds Conversion time Guaranteed
• No Missing Codes over Operating Temperature Range
• Data Outputs Three-State TTL Compatible, other Logic Inputs and Output TTL and CMOS Compatible
• Choice of On-Chip or External Reference Voltage
• Ratiometric Operation
• Unipolar or Bipolar Input Ranges
• Complementary to ZN428 DAC

The ZN427 is an 8-bit successive approximation converter with three-state outputs to permit easy interfacing to a common data bus. The IC contains a voltage switching DAC, a fast comparator, successive approximation logic and a 2.56V precision bandgap reference, the use of which is pin optional to retain flexibility. An external fixed or varying reference may therefore be substituted, thus allowing ratiometric operation.
Only passive external components are required for the operation of the converter.

The ZN427 utilises the successive approximation technique. Upon receipt of a negative-going pulse at the WR input, the BUSY output goes low, the MSB is set to 1, and all other bits are set to 0, which produces an output voltage of VREF/2 from the DAC. This is compared to the input voltage VIN; a decision is made on the next negative clock edge to reset the MSB to 0 if VRef/2 > VIN or leave it set to 1 if VRef/2 < VIN.
Bit 2 is set to 1 on the same clock edge, producing an output from the DAC of VRef/4 or VRef/2 + VRef/4 depending on the state of the MSB. This voltage is compared to VIN, and on the next clock edge a decision is made regarding bit 2, whilst bit 3 is set to 1. This procedure is repeated for all eight bits. On the ninth negative clock edge, BUSY goes high indicating that the conversion is complete.
During a conversion, the RD input will generally be held high to keep the three-state buffers in their high impedance state. Data can be read out by taking RD high, thus enabling the three-state output. The readout is non-destructive. The BUSY output may be tied to the RD input to automatically enable the outputs when the data is valid.
For reliable operation of the converter, the start pulse applied to the WR input must meet specific timing criteria with respect to the converter clock; these are detailed in the timing diagram of Fig.3.

1. A conversion sequence is shown for the digital word 01100110. For clarity the three-state outputs are shown as being enabled during the conversion, but normal practice would be to disable them until the conversion was complete.
2. The BUSY output goes low during a conversion.  When BUSY goes high at the end of a conversion the output data is valid. In a microprocessor system the BUSY output can be used to generate an interrupt request when the conversion is complete.
3. In the timing diagram cross hatching indicates a 'don't care' condition.
4. The start pulse operates as an asynchronous (independent of clock) reset that sets the MSB output to 1 and sets all other outputs and the end of conversion flag to 0. This resetting occurs on the low-going edge of the start pulse and as long as WR is low the converter is inhibited.  Conversion commences on the first active (negative going) clock edge after the WR input has gone high again, when the MSB decision is made. A number of timing constraints thus supply to the start pulse.

(a) The minimum duration of the start pulse is 250ns, to allow reliable resetting of the converter logic circuits.
(b) There is no limit to the maximum duration of the start pulse.
(c) To allow the MSB to settle, at least 1.5µs must elapse between the negative going edge of the start pulse and the first active clock edge that indicates the MSB decision.
(d) To ensure reliable clocking, the positive-going edge of the start pulse should not occur within 200ns of an active (negative-going) clock edge. The ideal place for the positive-going edge of the start pulse is coincident with a positive-going clock edge. As a special case of the above conditions that start pulse may be synchronous with a negative-going clock pulse.

The actual method of generating the clock signal and synchronising it to the start conversion system in which the ZN427 is incorporated.
When used with a microprocessor the ZN427 can be treated as RAM and can be assigned a memory address using an address decoder. If the µP clock is used to drive the ZN427 and the µP write pulse meets the ZN427 timing criteria with respect to the µP clock then generating the start pulse is simply a matter of gating the decoded address with the microprocessor write pulse. Whilst the conversion is being performed the microprocessor can perform other instructions or No operation (NOP); when the conversion is complete the outputs can be enabled onto the bus by gating the decoded address with the read pulse. A timing diagram for this sequence of operation is given in Fig.4.
An advantage of using the microprocessor clock is that the conversion time is known precisely in terms of machine cycles. the data outputs may therefore be read after a fixed delay of at least nine clock cycles after the end of the WR pulse, when the conversion will be complete.
Alternatively the read operation may be initiated by using the BUSY output to generate interrupt request.
In some systems, for example single-chip microcomputers such as the 8048, this simple method may not be feasible for one or more of the following reasons:
(a) The MPU clock is not available externally.
(b) The clock frequency is too high.
(c) The write pulse timing criteria make it unsuitable for direct use as a start conversion pulse.
If any of these conditions apply then the self-synchronising clock circuit of Fig.5a is recommended.

N1 is connected as an astable multivibrator which, when the BUSY output is high, is inhibited by the output of N2 holding one of its inputs low. The start conversion pulse resets the BUSY flag and N1 begins to oscillate. When the conversion is complete BUSY goes high and the clock is inhibited.

Since the start pulse starts the clock it may occur at any time. The only constraints on the start pulse are that it must be longer than 250ns but at least 200ns shorter than the first clock pulse. The first clock pulse is in fact longer than the rest since C1 starts from a fully charged condition whereas on subsequent cycles it changes between the upper and lower threshold (VT+ and VT) of the Schmitt trigger.